Group III-nitride based high electron mobility transistors (HEMTs) are attracting significant interest for microwave and power switching applications. The power capability and reliability of III-nitride transistors is strongly dependent on the channel temperature and/or junction temperature of the III-nitride transistor. A high channel and/or junction temperature can degrade the performance of the transistor due to an increase in phonon scattering and also accelerate failure mechanism. The thermal conductive of the substrate strongly affects the thermal resistance from the channel and junction region to heat sink on the bottom side of the device. Thus, it is advantages to use a high thermal conductivity substrate to minimize the channel and junction temperature. Diamond can have thermal conductivities of approximately 2000 W/mK and is thus a desirable substrate to reduce the thermal resistance from the channel region to the heat sink.
A semiconductor integrated within one or more diamond material layers in accordance with the present invention can provide significantly improved thermal management, including extremely high thermal conductivity for very high-power GaN transistors, which can enable a transistor with high microwave output power levels, a light emitting device with high light emission flux, or a power switching devices with high current capability while maintaining the device channel or junction temperature at a temperature which will not accelerate reliability failure mechanisms. Alternately, the improved thermal management provided by integrated diamond layers can lower the channel and junction temperature, providing improved reliability.
Diamond has a very low thermal expansion coefficient of approximately 1.0×10−6 K−1 at 300 C. Gallium nitride has a thermal expansion coefficient of approximately 5.6×10−6 K−1 at 300 C. Thus, there is a very large difference in thermal expansion coefficients between diamond and gallium nitride.
The epitaxial material for a III-nitride HEMT are often grown to have a gallium-polar (metal-polar) (0001) surface but can be grown to have a nitrogen polar GaN (000″1) surface. The gallium-polar (metal-polar) (0001) surface and the nitrogen-polar (000″1) surfaces have negative and positive fixed spontaneous polarization sheet charges, respectively. The III-nitride epitaxial material are typically grown on a sapphire, silicon carbide, silicon, or gallium nitride substrate. For the sapphire, silicon carbide, and silicon substrates, a III-nitride nucleation layer is typically initially grown on the substrate to obtain III-nitride epitaxial material growth with a gallium-polar (metal-polar) (0001) surface. The III-nitride nucleation layer is often a low temperature grown AlN layer but can also be high temperature AlN layer, TiN, nanocrystalline material, or other material known to those skilled in the art.
In the III-nitride HEMT, a barrier material layer grown on a GaN surface with gallium-polar (0001) surface will induce a two-dimensional electron gas (2DEG) at the interface of the barrier material layer with the GaN material due to strain induced piezoelectric effect and/or the spontaneous polarization effect at the barrier material layer/GaN interface. Because of the strain induced piezoelectric effect, the magnitude and type of strain (whether tensile or compressive) can influence the density of carriers in the 2DEG and the threshold voltage of the III-nitride HEMT device. The strain at the barrier material layer/GaN interface is thus an important parameter for III-nitride HEMT devices.
An important parameter for III-Nitride High Electron Mobility Transistors (HEMT) is the thermal boundary resistance at the III-Nitride semiconductor material/substrate interface. The substrate for III-Nitride HEMTs are typically sapphire, silicon carbide, or silicon. The thermal boundary resistance is increased by the presence of an III-nitride nucleation layer at the III-nitride/substrate interface and also the defective III-nitride semiconductor material adjacent to the III-nitride nucleation layer. A. Manoi, J. W. Pomeroy, M. Killat, and M. Kuball, “Benchmarking of Thermal Boundary Resistance In AlGaN/GaN HEMTs on SiC Substrates: Implications of the Nucleation Layer Microstructure,” IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 12, DECEMBER 2010, pp. 1395-1397.
Fusion or direct bonding directly bonds two wafers that are initially only connected by the weak atomic forces (van der Waals forces) of hydroxyl (OH) groups in the interface (borderline) layer between the two wafers. By subsequently applying heat, covalent bonds are formed between the two wafers. This is a very strong, non-soluble bonding of the two wafers and is suitable for high temperature processing of the wafer pair. The surface of wafers will typically be prepared to be hydrophilic for direct or fusion bonding, especially if the wafers have a dielectric or oxide layer on the surface. It is also possible to have hydrophobic wafer direct bonding for the case that a silicon surface is hydrogen terminated. The surface of the two wafers can be exposed to a plasma to achieve improved direct or fusion bonding. Another type of bonding is adhesive bonding which typically uses polymers to adhere two wafers together. Adhesive or glue bonding is typically not suitable for high temperature processing because gases evolve from the polymer upon exposure to high temperature and the gases form bubbles in the adhesive layer which is undesirable for bonded wafer pairs.
Previous methods to integrate diamond on the second side of semiconductor material have involved bonding semiconductor material to a diamond substrate. The most common approach to bond the diamond substrate to the semiconductor material has involved using a bonding material adhere the semiconductor material to the diamond substrate. The use of the bonding material increases the thermal resistance from semiconductor material to the diamond substrate because of both the lower thermal conductivity of the bonding material compared to diamond and also the additional material interfaces increase the thermal resistance by causing additional phonon scattering. See, e.g., D. Francis, F. Ejeckam, J. Wasserbauer, and D. Babic, “Semiconductor devices having gallium nitride epilayers on diamond substrate, U.S. Pat. No. 8,283,672, Oct. 9, 2012; D. Francis, F. Ejeckam, J. Wasserbauer, D. Babic, “Method for manufacturing semiconductor devices having gallium nitride epilayers on diamond substrates,” U.S. Pat. No. 8,283,189, Oct. 9, 2012; D. Francis, F. Ejeckam, J. Wasserbauer, D. Babic, “Semiconductor devices having gallium nitride epilayers on diamond substrates,” U.S. Pat. No. 7,595,507, Sep. 29, 2009; K. Cheng, M. Leys, S. Degroote, “Method for forming a group III nitride material on a silicon substrate,” U.S. Pat. No. 7,989,925, Aug. 2, 2011; and F. J. Kub and K. D. Hobart, “Gate after diamond transistor,” U.S. Pat. No. 8,039,301, Oct. 18, 2011.